Logical decision circuits



Jan. 25, 1966 L. D. SPRINGER LOGICAL DECISION CIRCUITS Original FiledJune 27, 1958 I374 335 W4 OR V 3 AND NOT DIVISIBLE 8 NOT J (NO GO) 1 1 V|40| I380 Ages '42] x533 1 1 T V l4l9 0R I388 ql387 V I *1 NOT V I422I389 A372 I402 CLOCK F39 IA 9 c,

ABC Is NOT DIVISIBLE. IF:

(I) A=O AND 2) a=o ORI AND(3) B=0 OR c=o 0R1 INVENTOR LAMAR D. SPRINGERHIS ATTORNEYS United States Patent O LOGICAL DECISION CIRCUITS Lamar D.Springer, West Carrollton, Ohio, assignor to The National Cash RegisterCompany, Dayton, Ohio, a corporation of Maryland Original applicationJune 27, 1958, Ser. No. 744,977, now Patent No. 3,067,938, dated Dec.11, 1962. Divided and this application May 1, 1962, Ser. No. 191,698

2 Claims. (Cl. 235-173) This invention relates to logical decisioncircuits and, more specifically, to a logical decision circuit of thetype which produces an output signal upon the coincident presence of oneof preselected alternative combinations of input signals.

This application is a division of United States patent applicationSerial No. 744,977, filed June 27, 1958, now Patent No. 3,067,938 datedDecember 11, 1962.

In electronic computer and similar applications, it is frequentlynecessary to provide for a signal pulse upon the occurrence ofpreselected alternative combinations of signals. Conventional AND gatesare senstitive to only one specific preselected combination of inputsignals but are incapable of distinguishing two or more combinations.Therefore, in applications which require production of an output signalupon the occurrence of any one of two ore more alternative combinationsof input signals, it is necessary to provide a logical decision circuitwhich is sensitive to any one of the preselected alternativecombinations and no others.

It is, therefore, an object of this invention to provide an improvedlogical decision circuit.

It is another object of this invention to provide an improved logicaldecision circuit which is sensitive to two or more preselectedcombinations of input signals and produces an output signal in responsethereto.

It is a further object of this invention to provide a logical decisioncircuit comprising a novel combination of conventional AND, OR, and NOTcircuits.

In accordance with this invention, conventional AND, OR, and NOTcircuits are uniquely combined and interconnected in such a manner as toprovide a logical decision circuit which will produce an output signalupon the coincident presence of its input terminals of any one of aplurality of different preselected alternative combinations of inputsignals.

For a better understanding of the present invention, together withfurther objects, advantages, and features thereof, reference is made tothe following description and accompanying drawing, in which:

FIGURE 1 is a block-type schematic diagram of the logical decisioncircuit of this invention, and

FIGURE 2 represents the preselected combination of signals to which thelogical decision circuit of FIGURE 1 is sensitive.

In the United States patent application hereinabo've identified, ofwhich this application is a division, a practical application of thenovel logic decision circuitry of this invention was described in detailrelative to providing novel controls in an electronic Sterlingmultiplier. However it is to be specifically understood that this novelcircuitry may be used with other applications and is not to be construedas being limited to that specific embodiment.

As the details of the individual conventional AND, OR, and NOT elementsform no part of this invention and are familiar to those skilled in theart, they have been shown in block form in FIGURE 1, where the logicdecision circuitry of this invention which will produce an output pulseunder the conditions set forth in FIG- URE 2 is schematically set forth.

During the operating cycle of the Sterling multiplier device with whichthis circuit was employed, it was necesice sary to perform a divisionoperation involving a series of successive substractions for the purposeof extracting from a lower denominate order accumulator all integralunits of the next higher denominate order. For example, at theconclusion of the multiplying operation, all integral shilling unitswere extracted from the pence accumulator by successively subtracting12, the number of pence in a shilling, until less than 12 pence remainedin the pence accumulator. So that this extraction operation may besuccessively applied to the next higher denominate order accumulators,it was necessary to produce a not divisible signal when less than anintegral unit of a higher denominate order remained in the next lowerdenominate order accumulator. It was for this purpose that the noveldecision circuit of this invention was developed.

Each of the accumulators of the Sterling multiplier is composed of aseparate recycling binary type decimal counter, termed order banks, foreach the units, tong-hundreds, thousands, etc, decimal orders of value.Referring to FIGURE 2 ,the pence accumulator order banks arediagrammatically represented as a series of blocks wherein the blockslabeled A, B, and C are the hundreds, tens, and units order banks,respectively. Therefore any value of pence between 0 and 999 may bestored in these three banks. The total quantity stored in these banks isnot d-ivisab'le by 12 only if the quan tity stored in A bank is 0,indicating the total quantity stored to be less than 100, and thequantity stored in the B bank is 0 or 1, indicating the total quantitystored to be less than 20, and the quantity stored in the C bank is 0 or1, indicating the total quantity stored to be less than 12.

Each bank of the accumulator circuits is arranged to supply anegative-going direct current bias potential upon the readout leadcorresponding to the value of the stored quantity. Therefore, to providea logic decision circuit which is sensitive to all of the combination ofinput signals required to fulfill the not divisible conditions set forthin FIGURE 2, the input terminals of the respective NOT circuits must beconnected to the 0 readout lead 1317 of the pence accumulator A bank; tothe 0 readout lead 1374 and the 1 readout lead 1380 of the penceaccumulator B bank; and to the O readout lead 1388 and the 1 readoutlead 1389 of the pence accumulator C bank, as indicated.

The NOT circuits may be vacuum tube triodes having the cathodesconnected to ground and the anodes connected to a source of positivepotential which are arranged to be biased either to cut-01f or tosaturation. Common clock lead 1372 is connected to the control grid ofeach of the triodes, and the readout leads from the accumulator areconnected to the control grid of the respective triodes. In the absenceof a negative-going direct-current bias potential on the accumulatorreadout leads, the positive-going clock pulses applied tothe controlgrids are ineffective because the triode is biased to saturation. Withthe presence of a negative-going bias potential on any of theaccumulator readout leads, the associated triode is thereby biased tocut-01f, and the positive-going clock pulses applied to the grids are ofsufficient magnitude to overcome the negative bias, thereby causing thetriode to conduct over the duration of the clock pulse. This results ina negative polarity signal at the anode terminal of the triode, which istaken oil? through a capacitor.

The A0 readout lead 1317 extends through NOT circuit 1324, which has anoutput lead 1411, to AND circuit 1333, which is arranged to supply anot-divisible (or NO GO) signal whenever all three of its inputs arepresent and of a negative polarity. The NOT circuit 3 1324 of the Areadout lead 1317 also receives a positivegoing clock pulse over commonlead 1372. Vhenever the content of the A bank is O, a negative-goingD.C. bias is supplied to the grid of the triode of NOT circuit 1324.This triode is either saturated or cut off according to the DC. biassupplied by the readout lead 1317. Hence, the NOT circuit 1324 isreceptive to the clock pulse when bank A is storing a 0 count, therebypermitting a negative-going pulse to appear on output lead 1411. Thepresence of the pulse on the lead 1411 indicates that condition (1) istrue; i.e., 11:0. However, this is but one of three inputs to the ANDcircuit 1333.

Similarly, in condition (2), if the B0 readout lead 1374 from the B bankindicates a content of 0 in the B bank, a negative pulse is derived fromthe NOT circuit 1379 and applied over output lead 1414 to the OR circuit1481. However, if the content of the B bank is 1, the readout 1380provides a negative-going potential to the NOT circuit 1385 to produce anegative pulse on output lead 1415, which also extends to the OR circuit1401. Hence, according to condition (2), if the B bank is storing eithera 0 count or a 1 count, a negative pulse appears on the output lead 1418from the OR circuit 1401 -for application to the AND circuit 1333.

The first part of condition (3) is that the B bank must be storing a 0count. Hence, the lead 1421 extends from the lead 1414, which is theoutput lead for the NOT circuit 1379 of the B0 readout lead 1374, to theOR circuit 1482. The OR circuit 1402 will also receive a pulse if the Cbank is storing a 0 count or a 1 count. The 0 readout 1388 applies anegative-going DC. bias to the NOT circuit 1386 to produce anegative-going pulse on the output lead 1419 as an input to the ORcircuit 1402, whenever the count in the C bank is 0. Similarly, a 1count in the C bank provides a negativegoing bias over the 1 readoutlead 1389 to the NOT circuit 1387 for developing a negative-going pulseon the output lead 1420 for application to the OR circuit 1402.Obviously, pulses cannot be obtained from both of the C0 and C1 readoutleads at the same time, because the count of the C bank cannot be both 0and 1. However, the OR circuit 1482 requires only a single input toobtain an output negative pulse on the lead 1422 for the AND circuit1333.

The AND circuit 1333 is a Rossi type circuit, wherein three triode tu'besections are normally conducting, and only the simultaneous applicationof three negative-going pulses to the grid circuits of these tubes willincrease the common anode potential to produce a positive output signalindicative of a not-divisible condition.

Under the conditions hereinabove described, the requirement of threenegative-polarity pulses coincidentally applied to the three inputterminals of the AND gate 1333 to produce an output signal therefrom issatisfied. The signal thus produced may be directed to other cir- 4.cuitry and used to initiate a variety of additional functions asrequired.

While a single embodiment of the present invention has been shown anddescribed, it will be obvious to those skilled in the art that variousmodifications and substitutions may be made without departing from thespirit of the invention, which is to be limited only within the scope ofthe following claims:

What is claimed is:

1. A logical decision circuit comprising, in combination, an AND outputcircuit for receiving a first input lead which includes a NOT circuit;second and third input leads terminating in an OR circuit via a NOTcircuit in each lead; a common lead from said OR circuit to the ANDcircuit; fourth and fifth input leads terminating in a further ORcircuit via a NOT circuit in each lead; said further OR circuitreceiving a connection via the NOT circuit from said second input lead;and a further common lead from said further OR circuit to the ANDcircuit.

2. A logical decision circuit comprising, in combination, an AND outputelement; a plurality of input leads for said decision circuit; NOTelements connected in each of said leads; a clock input circuitextending to each NOT element; a first OR element; a first combinationof said input leads as determined by the decision requirementsterminating at said OR element; a further connection from said ORelement to said AND element; a further OR element; a differentcombination of said input leads as determined by the decisionrequirements terminating at said further OR element; a further commonlead from said further OR element to said AND element; and a connectionfrom one lead of said first combination to said further OR element via aNOT circuit.

7 References Cited by the Examiner UNITED STATES PATENTS 4/1957 Hansen235-173 X OTHER REFERENCES Pages 126-7, August 1956, Barnes, L. A.:Boolean Algebra for Switching Circuits, Conover Mast Publications, 205E. 42nd St., New York, N.Y., Electrical Manufacturing.

Pages 548, 1958, Truxal: Control Engineers Handbook, McGraw-Hill BookCompany, New York.

Page 67, 1957, Richards: Digital Computer Components and Circuits, D.Van Nostrand Company, Inc., 257 Fourth Ave., New York 10, N.Y.

Chapter 6, 1951, Keister, Ritchie and Washburn: The Design of SwitchingCircuits, D. Van Nostrand Company, Inc., 257 Fourth Avenue, New York, N.Y.

ROBERT C. BAILEY, Primary Examiner.

MALCOLM A. MORRISON, Examiner.

2. A LOGICAL DECISION CIRCUIT COMPRISING, IN COMBINATION, AN AND OUTPUTELEMENT; A PLURALITY OF INPUT LEADS FOR SAID DECISION CIRCUIT; NOTELEMENTS CONNECTED IN EACH OF SAID LEADS; A CLOCK INPUT CIRCUITEXTENDING TO EACH NOT ELEMENT; A FIRST OR ELEMENT; A FIRST COMBINATIONOF SAID INPUT LEADS AS DETERMINED BY THE DECISION REQUIREMENTSTERMINATING AT SAID OR ELEMENT; A FURTHER CONNECTION FROM SAID ORELEMENT TO SAID AND ELEMENT; A FURTHER OR ELEMENT; A DIFFERENTCOMBINATION OF SAID INPUT LEADS AS DETERMINED BY THE DECISIONREQUIREMENTS TERMINATING AT SAID FURTHER OR ELEMENT; A FURTHER COMMONLEAD FROM SAID FURTHER OR ELEMENT TO SAID AND ELEMENT; AND A CONNECTIONFROM ONE LEAD OF SAID FIRST COMBINATION TO SAID FURTHER OR ELEMENT VIA ANOT CIRCUIT.